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The co-processor is implemented mainly in VHDL, but the N-bit Adder is designed in Verilog. The Verilog code for the N-bit Adder will be instantiated later in a. Vhdl code for serial adder with. Sequential multiplier VERILOG xilinx code for 8-bit serial adder 8 bit fir. Serial Building, Data-path Functions.
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1. Homework Statement
My homework is to design a Serial Adder in Verilog using a shift register module, a full adder module, and a D Flip-Flop module.
I know my full adder and flip flop modules are correct, but I am not so sure about my shift register. The shift register is 8 bits:
Inputs for the shift register are: Si, CLK, Reset
Outputs for the shift register are: So, D7 through D0 (one for each bit of the register)
Also, if anyone can give me a hint as to how I can approach designing a test bench would be extremely helpful.
3. The Attempt at a Solution
My homework is to design a Serial Adder in Verilog using a shift register module, a full adder module, and a D Flip-Flop module.
I know my full adder and flip flop modules are correct, but I am not so sure about my shift register. The shift register is 8 bits:
Inputs for the shift register are: Si, CLK, Reset
Outputs for the shift register are: So, D7 through D0 (one for each bit of the register)
Also, if anyone can give me a hint as to how I can approach designing a test bench would be extremely helpful.
3. The Attempt at a Solution